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Freescale Semiconductor /MKE15D7 /SIM /CLKDIV1

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Interpret as CLKDIV1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (00)OUTDIV5 0RESERVED 0 (00)OUTDIV4 0RESERVED 0 (00)OUTDIV3 0RESERVED 0 (00)OUTDIV2 0RESERVED 0 (00)OUTDIV1 0RESERVED

OUTDIV4=00, OUTDIV2=00, OUTDIV3=00, OUTDIV5=00, OUTDIV1=00

Description

System Clock Divider Register 1

Fields

RESERVED

no description available
OUTDIV5

Clock 5 output divider value

0 (00): ICSOUT divided by 1.

1 (01): ICSOUT divided by 2.

2 (10): Reserved.

3 (11): ICSOUT divided by 4.
RESERVED

no description available
OUTDIV4

Clock 4 output divider value

0 (00): ICSOUT divided by 2.

1 (01): ICSOUT divided by 4.

2 (10): Reserved.

3 (11): ICSOUT divided by 8.
RESERVED

no description available
OUTDIV3

Clock 3 output divider value

0 (00): ICSOUT divided by 4, it is valid only when Maxclk = 36 MHz.

1 (01): ICSOUT divided by 8.

2 (10): Reserved.

3 (11): ICSOUT divided by 16, it is valid only when Maxclk = 36 MHz.
RESERVED

no description available
OUTDIV2

Clock 2 output divider value

0 (00): ICSOUT divided by 2.

1 (01): ICSOUT divided by 4.

2 (10): Reserved.

3 (11): ICSOUT divided by 8.
RESERVED

no description available
OUTDIV1

Clock 1 output divider value

0 (00): ICSOUT Divided by 1.

1 (01): ICSOUT Divided by 2.

2 (10): Reserved.

3 (11): ICSOUT Divided by 4.
RESERVED

no description available

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data